// ******************************************************************** // * 16 x 16 bits array multiplier with an improved propagation * // * exorand technology (registered trademark) * // * www.exorand.com * // * Copyright 2017 * // * * // ******************************************************************** // This Verilog module implements a 16 x 16 bits binary multiplication // Result of the multiplication array is expresses in BSCB form and // converted to standard binary form with a BSCB Ripple Carry Adder chain module Mult_16x16_BSCB(x, y, P); input [16:1] x, y; output [32:1] P; wire NULL, VCC, rca_in, init_col1; wire [32:1] P; wire [16:1] l_in_01, k_in_01, e_in_01, h_in_01, l_out_01, k_out_01; wire [16:1] l_in_02, k_in_02, e_in_02, h_in_02, l_out_02, k_out_02; wire [16:1] l_in_03, k_in_03, e_in_03, h_in_03, l_out_03, k_out_03; wire [16:1] l_in_04, k_in_04, e_in_04, h_in_04, l_out_04, k_out_04; wire [16:1] l_in_05, k_in_05, e_in_05, h_in_05, l_out_05, k_out_05; wire [16:1] l_in_06, k_in_06, e_in_06, h_in_06, l_out_06, k_out_06; wire [16:1] l_in_07, k_in_07, e_in_07, h_in_07, l_out_07, k_out_07; wire [16:1] l_in_08, k_in_08, e_in_08, h_in_08, l_out_08, k_out_08; wire [16:1] l_in_09, k_in_09, e_in_09, h_in_09, l_out_09, k_out_09; wire [16:1] l_in_10, k_in_10, e_in_10, h_in_10, l_out_10, k_out_10; wire [16:1] l_in_11, k_in_11, e_in_11, h_in_11, l_out_11, k_out_11; wire [16:1] l_in_12, k_in_12, e_in_12, h_in_12, l_out_12, k_out_12; wire [16:1] l_in_13, k_in_13, e_in_13, h_in_13, l_out_13, k_out_13; wire [16:1] l_in_14, k_in_14, e_in_14, h_in_14, l_out_14, k_out_14; wire [16:1] l_in_15, k_in_15, e_in_15, h_in_15, l_out_15, k_out_15; wire [16:1] l_in_16, k_in_16, e_in_16, h_in_16, l_out_16, k_out_16; wire [16:1] l_in_17, k_in_17, e_in_17, h_in_17, l_out_17, k_out_17; wire [16:1] l_in_18, k_in_18, e_in_18, h_in_18, l_out_18, k_out_18; wire [16:1] ec_in_18, hc_in_18, hb_in_01, enot_in_17, hnot_in_17; wire [32:1] u_BSCB, r_BSCB; assign NULL = 0; assign VCC = 1; // Computation of the multiplicator rows e and h // --------------------------------------------- Init Init_row_01(NULL, y[1], x, e_in_01, hb_in_01); // compute for first column, inversion h Mxor2 FirstCol(x[2], y[1], init_col1); Init Init_row_02(NULL, y[2], x, e_in_02, h_in_02); Init Init_row_03(y[1], y[3], x, e_in_03, h_in_03); Init Init_row_04(y[2], y[4], x, e_in_04, h_in_04); Init Init_row_05(y[3], y[5], x, e_in_05, h_in_05); Init Init_row_06(y[4], y[6], x, e_in_06, h_in_06); Init Init_row_07(y[5], y[7], x, e_in_07, h_in_07); Init Init_row_08(y[6], y[8], x, e_in_08, h_in_08); Init Init_row_09(y[7], y[9], x, e_in_09, h_in_09); Init Init_row_10(y[8], y[10], x, e_in_10, h_in_10); Init Init_row_11(y[9], y[11], x, e_in_11, h_in_11); Init Init_row_12(y[10], y[12], x, e_in_12, h_in_12); Init Init_row_13(y[11], y[13], x, e_in_13, h_in_13); Init Init_row_14(y[12], y[14], x, e_in_14, h_in_14); Init Init_row_15(y[13], y[15], x, e_in_15, h_in_15); Init Init_row_16(y[14], y[16], x, e_in_16, h_in_16); // assuming y[17]=0 Init Init_row_17(y[15], NULL, x, e_in_17, h_in_17); Init Init_row_18(y[16], NULL, x, e_in_18, h_in_18); // Rows computation cells // ------- line 1 -------------------------------------------------------- // Initialization line 1 // --------------------- Mxor2 Init_l_01(y[1], x[2], l_in_01[1]); Mxor2 Init_l_02(y[2], x[3], l_in_01[2]); Mxor2 Init_l_03(y[3], x[4], l_in_01[3]); Mxor2 Init_l_04(y[4], x[5], l_in_01[4]); Mxor2 Init_l_05(y[5], x[6], l_in_01[5]); Mxor2 Init_l_06(y[6], x[7], l_in_01[6]); Mxor2 Init_l_07(y[7], x[8], l_in_01[7]); Mxor2 Init_l_08(y[8], x[9], l_in_01[8]); Mxor2 Init_l_09(y[9], x[10], l_in_01[9]); Mxor2 Init_l_10(y[10], x[11], l_in_01[10]); Mxor2 Init_l_11(y[11], x[12], l_in_01[11]); Mxor2 Init_l_12(y[12], x[13], l_in_01[12]); Mxor2 Init_l_13(y[13], x[14], l_in_01[13]); Mxor2 Init_l_14(y[14], x[15], l_in_01[14]); Mxor2 Init_l_15(y[15], x[16], l_in_01[15]); Mxor2 Init_l_16(y[16], VCC, l_in_01[16]); // initialisation of k, first line // MSB k value of first line is set to 1 assign k_in_01[16:1] = 16'b1000000000000000; assign h_in_01[16:1] = {hb_in_01[16:2], init_col1}; MLine LINE01(l_in_01, k_in_01, e_in_01, h_in_01, l_out_01, k_out_01); // ------- line 2 -------------------------------------------------------- // initialisation of k, second line Mand2 Init_k2_01(y[1], ~x[2], k_in_02[1]); Mand2 Init_k2_02(y[2], ~x[3], k_in_02[2]); Mand2 Init_k2_03(y[3], ~x[4], k_in_02[3]); Mand2 Init_k2_04(y[4], ~x[5], k_in_02[4]); Mand2 Init_k2_05(y[5], ~x[6], k_in_02[5]); Mand2 Init_k2_06(y[6], ~x[7], k_in_02[6]); Mand2 Init_k2_07(y[7], ~x[8], k_in_02[7]); Mand2 Init_k2_08(y[8], ~x[9], k_in_02[8]); Mand2 Init_k2_09(y[9], ~x[10], k_in_02[9]); Mand2 Init_k2_10(y[10], ~x[11], k_in_02[10]); Mand2 Init_k2_11(y[11], ~x[12], k_in_02[11]); Mand2 Init_k2_12(y[12], ~x[13], k_in_02[12]); Mand2 Init_k2_13(y[13], ~x[14], k_in_02[13]); Mand2 Init_k2_14(y[14], ~x[15], k_in_02[14]); Mand2 Init_k2_15(y[15], ~x[16], k_in_02[15]); // MSB k value of second line is set to 1 assign k_in_02[16] = VCC; assign l_in_02[16:1] = {~y[1], l_out_01[16:2]}; MLine LINE02(l_in_02, k_in_02, e_in_02, h_in_02, l_out_02, k_out_02); // ------- line 3 -------------------------------------------------------- assign l_in_03[16:1] = {~y[2], l_out_02[16:2]}; assign k_in_03[16:1] = {1'b1, k_out_01[16:2]}; MLine LINE03(l_in_03, k_in_03, e_in_03, h_in_03, l_out_03, k_out_03); // ------- line 4 -------------------------------------------------------- assign l_in_04[16:1] = {~y[3], l_out_03[16:2]}; assign k_in_04[16:1] = {1'b1, k_out_02[16:2]}; MLine LINE04(l_in_04, k_in_04, e_in_04, h_in_04, l_out_04, k_out_04); // ------- line 5 -------------------------------------------------------- assign l_in_05[16:1] = {~y[4], l_out_04[16:2]}; assign k_in_05[16:1] = {1'b1, k_out_03[16:2]}; MLine LINE05(l_in_05, k_in_05, e_in_05, h_in_05, l_out_05, k_out_05); // ------- line 6 -------------------------------------------------------- assign l_in_06[16:1] = {~y[5], l_out_05[16:2]}; assign k_in_06[16:1] = {1'b1, k_out_04[16:2]}; MLine LINE06(l_in_06, k_in_06, e_in_06, h_in_06, l_out_06, k_out_06); // ------- line 7 -------------------------------------------------------- assign l_in_07[16:1] = {~y[6], l_out_06[16:2]}; assign k_in_07[16:1] = {1'b1, k_out_05[16:2]}; MLine LINE07(l_in_07, k_in_07, e_in_07, h_in_07, l_out_07, k_out_07); // ------- line 8 -------------------------------------------------------- assign l_in_08[16:1] = {~y[7], l_out_07[16:2]}; assign k_in_08[16:1] = {1'b1, k_out_06[16:2]}; MLine LINE08(l_in_08, k_in_08, e_in_08, h_in_08, l_out_08, k_out_08); // ------- line 9 -------------------------------------------------------- assign l_in_09[16:1] = {~y[8], l_out_08[16:2]}; assign k_in_09[16:1] = {1'b1, k_out_07[16:2]}; MLine LINE09(l_in_09, k_in_09, e_in_09, h_in_09, l_out_09, k_out_09); // ------- line 10 -------------------------------------------------------- assign l_in_10[16:1] = {~y[9], l_out_09[16:2]}; assign k_in_10[16:1] = {1'b1, k_out_08[16:2]}; MLine LINE10(l_in_10, k_in_10, e_in_10, h_in_10, l_out_10, k_out_10); // ------- line 11 -------------------------------------------------------- assign l_in_11[16:1] = {~y[10], l_out_10[16:2]}; assign k_in_11[16:1] = {1'b1, k_out_09[16:2]}; MLine LINE11(l_in_11, k_in_11, e_in_11, h_in_11, l_out_11, k_out_11); // ------- line 12 -------------------------------------------------------- assign l_in_12[16:1] = {~y[11], l_out_11[16:2]}; assign k_in_12[16:1] = {1'b1, k_out_10[16:2]}; MLine LINE12(l_in_12, k_in_12, e_in_12, h_in_12, l_out_12, k_out_12); // ------- line 13 -------------------------------------------------------- assign l_in_13[16:1] = {~y[12], l_out_12[16:2]}; assign k_in_13[16:1] = {1'b1, k_out_11[16:2]}; MLine LINE13(l_in_13, k_in_13, e_in_13, h_in_13, l_out_13, k_out_13); // ------- line 14 -------------------------------------------------------- assign l_in_14[16:1] = {~y[13], l_out_13[16:2]}; assign k_in_14[16:1] = {1'b1, k_out_12[16:2]}; MLine LINE14(l_in_14, k_in_14, e_in_14, h_in_14, l_out_14, k_out_14); // ------- line 15 -------------------------------------------------------- assign l_in_15[16:1] = {~y[14], l_out_14[16:2]}; assign k_in_15[16:1] = {1'b1, k_out_13[16:2]}; MLine LINE15(l_in_15, k_in_15, e_in_15, h_in_15, l_out_15, k_out_15); // ------- line 16 -------------------------------------------------------- assign l_in_16[16:1] = {~y[15], l_out_15[16:2]}; assign k_in_16[16:1] = {1'b1, k_out_14[16:2]}; MLine LINE16(l_in_16, k_in_16, e_in_16, h_in_16, l_out_16, k_out_16); // ------- line 17 -------------------------------------------------------- // e eand h are inverted except for the last position as the diagonal values are already inverted assign l_in_17[16:1] = {~y[16], l_out_16[16:2]}; assign k_in_17[16:1] = {1'b1, k_out_15[16:2]}; assign enot_in_17[16:1] = {~e_in_17[16:2], e_in_17[1]}; assign hnot_in_17[16:1] = {~h_in_17[16:2], h_in_17[1]}; MLine LINE17(l_in_17, k_in_17, enot_in_17, hnot_in_17, l_out_17, k_out_17); // ------- line 18 -------------------------------------------------------- // assuming y[17]=0 assign l_in_18[16:1] = {NULL, l_out_17[16:2]}; assign k_in_18[16:1] = {1'b1, k_out_16[16:2]}; // computing e xor C (= k_out_17) // reset of the first value of C = k_out_17[1] // already taken into account in P[16] Mxor2 Comp_ec_01(e_in_18[1], VCC, ec_in_18[1]); Mxor2 Comp_ec_02(e_in_18[2], k_out_17[2], ec_in_18[2]); Mxor2 Comp_ec_03(e_in_18[3], k_out_17[3], ec_in_18[3]); Mxor2 Comp_ec_04(e_in_18[4], k_out_17[4], ec_in_18[4]); Mxor2 Comp_ec_05(e_in_18[5], k_out_17[5], ec_in_18[5]); Mxor2 Comp_ec_06(e_in_18[6], k_out_17[6], ec_in_18[6]); Mxor2 Comp_ec_07(e_in_18[7], k_out_17[7], ec_in_18[7]); Mxor2 Comp_ec_08(e_in_18[8], k_out_17[8], ec_in_18[8]); Mxor2 Comp_ec_09(e_in_18[9], k_out_17[9], ec_in_18[9]); Mxor2 Comp_ec_10(e_in_18[10], k_out_17[10], ec_in_18[10]); Mxor2 Comp_ec_11(e_in_18[11], k_out_17[11], ec_in_18[11]); Mxor2 Comp_ec_12(e_in_18[12], k_out_17[12], ec_in_18[12]); Mxor2 Comp_ec_13(e_in_18[13], k_out_17[13], ec_in_18[13]); Mxor2 Comp_ec_14(e_in_18[14], k_out_17[14], ec_in_18[14]); Mxor2 Comp_ec_15(e_in_18[15], k_out_17[15], ec_in_18[15]); Mxor2 Comp_ec_16(e_in_18[16], k_out_17[16], ec_in_18[16]); // computing h xor C (= k_out_16) // reset of the first value of C = k_out_17[1] Mxor2 Comp_hc_01(h_in_18[1], VCC, hc_in_18[1]); Mxor2 Comp_hc_02(h_in_18[2], k_out_17[2], hc_in_18[2]); Mxor2 Comp_hc_03(h_in_18[3], k_out_17[3], hc_in_18[3]); Mxor2 Comp_hc_04(h_in_18[4], k_out_17[4], hc_in_18[4]); Mxor2 Comp_hc_05(h_in_18[5], k_out_17[5], hc_in_18[5]); Mxor2 Comp_hc_06(h_in_18[6], k_out_17[6], hc_in_18[6]); Mxor2 Comp_hc_07(h_in_18[7], k_out_17[7], hc_in_18[7]); Mxor2 Comp_hc_08(h_in_18[8], k_out_17[8], hc_in_18[8]); Mxor2 Comp_hc_09(h_in_18[9], k_out_17[9], hc_in_18[9]); Mxor2 Comp_hc_10(h_in_18[10], k_out_17[10], hc_in_18[10]); Mxor2 Comp_hc_11(h_in_18[11], k_out_17[11], hc_in_18[11]); Mxor2 Comp_hc_12(h_in_18[12], k_out_17[12], hc_in_18[12]); Mxor2 Comp_hc_13(h_in_18[13], k_out_17[13], hc_in_18[13]); Mxor2 Comp_hc_14(h_in_18[14], k_out_17[14], hc_in_18[14]); Mxor2 Comp_hc_15(h_in_18[15], k_out_17[15], hc_in_18[15]); Mxor2 Comp_hc_16(h_in_18[16], k_out_17[16], hc_in_18[16]); MLine LINE18(l_in_18, k_in_18, ec_in_18, hc_in_18, l_out_18, k_out_18); // Final ripple carry adder chain // --------------------------------- // assembling the final BSCB result assign u_BSCB[4:1] = {l_out_05[1], l_out_04[1], l_out_03[1], l_out_02[1]}; assign u_BSCB[8:5] = {l_out_09[1], l_out_08[1], l_out_07[1], l_out_06[1]}; assign u_BSCB[12:9] = {l_out_13[1], l_out_12[1], l_out_11[1], l_out_10[1]}; assign u_BSCB[16:13] = {l_out_17[1], l_out_16[1], l_out_15[1], l_out_14[1]}; assign u_BSCB[20:17] = {l_out_18[4], l_out_18[3], l_out_18[2], l_out_18[1]}; assign u_BSCB[24:21] = {l_out_18[8], l_out_18[7], l_out_18[6], l_out_18[5]}; assign u_BSCB[28:25] = {l_out_18[12], l_out_18[11], l_out_18[10], l_out_18[9]}; assign u_BSCB[32:29] = {l_out_18[16], l_out_18[15], l_out_18[14], l_out_18[13]}; Mand2 Comp_Cy1(~x[1], ~x[2], rca_in); Mxor2 rca_xor(k_out_01[1], rca_in, r_BSCB[1]); assign r_BSCB[4:2] = {k_out_04[1], k_out_03[1], k_out_02[1]}; assign r_BSCB[8:5] = {k_out_08[1], k_out_07[1], k_out_06[1], k_out_05[1]}; assign r_BSCB[12:9] = {k_out_12[1], k_out_11[1], k_out_10[1], k_out_09[1]}; assign r_BSCB[16:13] = {k_out_16[1], k_out_15[1], k_out_14[1], k_out_13[1]}; assign r_BSCB[20:17] = {k_out_18[3], k_out_18[2], k_out_18[1], k_out_17[1]}; assign r_BSCB[24:21] = {k_out_18[7], k_out_18[6], k_out_18[5], k_out_18[4]}; assign r_BSCB[28:25] = {k_out_18[11], k_out_18[10], k_out_18[9], k_out_18[8]}; assign r_BSCB[32:29] = {k_out_18[15], k_out_18[14], k_out_18[13], k_out_18[12]}; // BSCB result is converted to standard binary form // Addition Diagonal RippleCarryAdderLine RCALine1(u_BSCB, r_BSCB, P); endmodule // -------------------------------------------------------------- // Functional Model of a line of 32 BSCB RCA adder INPUT:U,R // -------------------------------------------------------------- // use of gates without delay module RippleCarryAdderLine(u_Line, r_Line, P_Line); input [32:1] u_Line, r_Line; output [32:1] P_Line; wire [32:1] rca_out; wire NULL1; assign NULL1 = 0; RippleCarryAdder RCA01(NULL1, NULL1, u_Line[1], r_Line[1], rca_out[1], P_Line[1]); RippleCarryAdder RCA02(u_Line[1], rca_out[1], u_Line[2], r_Line[2], rca_out[2], P_Line[2]); RippleCarryAdder RCA03(u_Line[2], rca_out[2], u_Line[3], r_Line[3], rca_out[3], P_Line[3]); RippleCarryAdder RCA04(u_Line[3], rca_out[3], u_Line[4], r_Line[4], rca_out[4], P_Line[4]); RippleCarryAdder RCA05(u_Line[4], rca_out[4], u_Line[5], r_Line[5], rca_out[5], P_Line[5]); RippleCarryAdder RCA06(u_Line[5], rca_out[5], u_Line[6], r_Line[6], rca_out[6], P_Line[6]); RippleCarryAdder RCA07(u_Line[6], rca_out[6], u_Line[7], r_Line[7], rca_out[7], P_Line[7]); RippleCarryAdder RCA08(u_Line[7], rca_out[7], u_Line[8], r_Line[8], rca_out[8], P_Line[8]); RippleCarryAdder RCA09(u_Line[8], rca_out[8], u_Line[9], r_Line[9], rca_out[9], P_Line[9]); RippleCarryAdder RCA10(u_Line[9], rca_out[9], u_Line[10], r_Line[10], rca_out[10], P_Line[10]); RippleCarryAdder RCA11(u_Line[10], rca_out[10], u_Line[11], r_Line[11], rca_out[11], P_Line[11]); RippleCarryAdder RCA12(u_Line[11], rca_out[11], u_Line[12], r_Line[12], rca_out[12], P_Line[12]); RippleCarryAdder RCA13(u_Line[12], rca_out[12], u_Line[13], r_Line[13], rca_out[13], P_Line[13]); RippleCarryAdder RCA14(u_Line[13], rca_out[13], u_Line[14], r_Line[14], rca_out[14], P_Line[14]); RippleCarryAdder RCA15(u_Line[14], rca_out[14], u_Line[15], r_Line[15], rca_out[15], P_Line[15]); RippleCarryAdder RCA16(u_Line[15], rca_out[15], u_Line[16], r_Line[16], rca_out[16], P_Line[16]); RippleCarryAdder RCA17(u_Line[16], rca_out[16], u_Line[17], r_Line[17], rca_out[17], P_Line[17]); RippleCarryAdder RCA18(u_Line[17], rca_out[17], u_Line[18], r_Line[18], rca_out[18], P_Line[18]); RippleCarryAdder RCA19(u_Line[18], rca_out[18], u_Line[19], r_Line[19], rca_out[19], P_Line[19]); RippleCarryAdder RCA20(u_Line[19], rca_out[19], u_Line[20], r_Line[20], rca_out[20], P_Line[20]); RippleCarryAdder RCA21(u_Line[20], rca_out[20], u_Line[21], r_Line[21], rca_out[21], P_Line[21]); RippleCarryAdder RCA22(u_Line[21], rca_out[21], u_Line[22], r_Line[22], rca_out[22], P_Line[22]); RippleCarryAdder RCA23(u_Line[22], rca_out[22], u_Line[23], r_Line[23], rca_out[23], P_Line[23]); RippleCarryAdder RCA24(u_Line[23], rca_out[23], u_Line[24], r_Line[24], rca_out[24], P_Line[24]); RippleCarryAdder RCA25(u_Line[24], rca_out[24], u_Line[25], r_Line[25], rca_out[25], P_Line[25]); RippleCarryAdder RCA26(u_Line[25], rca_out[25], u_Line[26], r_Line[26], rca_out[26], P_Line[26]); RippleCarryAdder RCA27(u_Line[26], rca_out[26], u_Line[27], r_Line[27], rca_out[27], P_Line[27]); RippleCarryAdder RCA28(u_Line[27], rca_out[27], u_Line[28], r_Line[28], rca_out[28], P_Line[28]); RippleCarryAdder RCA29(u_Line[28], rca_out[28], u_Line[29], r_Line[29], rca_out[29], P_Line[29]); RippleCarryAdder RCA30(u_Line[29], rca_out[29], u_Line[30], r_Line[30], rca_out[30], P_Line[30]); RippleCarryAdder RCA31(u_Line[30], rca_out[30], u_Line[31], r_Line[31], rca_out[31], P_Line[31]); RippleCarryAdder RCA32(u_Line[31], rca_out[31], u_Line[32], r_Line[32], rca_out[32], P_Line[32]); endmodule // -------------------------------------------------------------- // Functional Model of a RCA adder (Ripple Carry Adder) INPUT:U,R // -------------------------------------------------------------- // use of gates without delay module RippleCarryAdder(Uin, Rin, U, R, Rout, S); input Uin, Rin, U, R; output Rout,S; wire x00x01, x01x03, x02x03; Mxor2wd X00(R,U,x00x01); Mxnor2wd X01(Uin,x00x01,x01x03); Mxor2wd X02(R,Rin,x02x03); Mand2wd X03(x01x03,x02x03,Rout); Mxor2wd X04(x02x03,U,S); endmodule // ----------------------------------------------- // Functional Model of a MCell Multiplication Cell // ----------------------------------------------- module MCell(l_in, k_in, e_in, h_in, l_out, k_out); input l_in, k_in, e_in, h_in; output l_out, k_out; wire x01x04, x02x04; Mxor2 X01(e_in,l_in, x01x04); Mxor2 X02(k_in, h_in,x02x04); Mxor2 X03(l_in,x02x04,l_out); Mand2 X04(x01x04,x02x04,k_out); endmodule // ---------------------------------------------- // Functional Model of a Line Multiplication Cell // ---------------------------------------------- module MLine(lb_in, kb_in, eb_in, hb_in, lb_out, kb_out); input [16:1] lb_in, kb_in, eb_in, hb_in; output [16:1] lb_out, kb_out; MCell M01(lb_in[1], kb_in[1], eb_in[1], hb_in[1], lb_out[1], kb_out[1]); MCell M02(lb_in[2], kb_in[2], eb_in[2], hb_in[2], lb_out[2], kb_out[2]); MCell M03(lb_in[3], kb_in[3], eb_in[3], hb_in[3], lb_out[3], kb_out[3]); MCell M04(lb_in[4], kb_in[4], eb_in[4], hb_in[4], lb_out[4], kb_out[4]); MCell M05(lb_in[5], kb_in[5], eb_in[5], hb_in[5], lb_out[5], kb_out[5]); MCell M06(lb_in[6], kb_in[6], eb_in[6], hb_in[6], lb_out[6], kb_out[6]); MCell M07(lb_in[7], kb_in[7], eb_in[7], hb_in[7], lb_out[7], kb_out[7]); MCell M08(lb_in[8], kb_in[8], eb_in[8], hb_in[8], lb_out[8], kb_out[8]); MCell M09(lb_in[9], kb_in[9], eb_in[9], hb_in[9], lb_out[9], kb_out[9]); MCell M10(lb_in[10], kb_in[10], eb_in[10], hb_in[10], lb_out[10], kb_out[10]); MCell M11(lb_in[11], kb_in[11], eb_in[11], hb_in[11], lb_out[11], kb_out[11]); MCell M12(lb_in[12], kb_in[12], eb_in[12], hb_in[12], lb_out[12], kb_out[12]); MCell M13(lb_in[13], kb_in[13], eb_in[13], hb_in[13], lb_out[13], kb_out[13]); MCell M14(lb_in[14], kb_in[14], eb_in[14], hb_in[14], lb_out[14], kb_out[14]); MCell M15(lb_in[15], kb_in[15], eb_in[15], hb_in[15], lb_out[15], kb_out[15]); MCell M16(lb_in[16], kb_in[16], eb_in[16], hb_in[16], lb_out[16], kb_out[16]); endmodule // ---------------------------------------------- // Functional Model of a row initialization line // ---------------------------------------------- module Init(y_in_1, y_in_3, xe_in, er_out, hr_out); input [16:1] xe_in; input y_in_1, y_in_3; output [16:1] er_out, hr_out; // e at lsb is inverted Mxor2 Xor_row_01(y_in_3, xe_in[1], er_out[1]); Mxnor2 Xor_row_02(y_in_3, xe_in[2], er_out[2]); Mxnor2 Xor_row_03(y_in_3, xe_in[3], er_out[3]); Mxnor2 Xor_row_04(y_in_3, xe_in[4], er_out[4]); Mxnor2 Xor_row_05(y_in_3, xe_in[5], er_out[5]); Mxnor2 Xor_row_06(y_in_3, xe_in[6], er_out[6]); Mxnor2 Xor_row_07(y_in_3, xe_in[7], er_out[7]); Mxnor2 Xor_row_08(y_in_3, xe_in[8], er_out[8]); Mxnor2 Xor_row_09(y_in_3, xe_in[9], er_out[9]); Mxnor2 Xor_row_10(y_in_3, xe_in[10], er_out[10]); Mxnor2 Xor_row_11(y_in_3, xe_in[11], er_out[11]); Mxnor2 Xor_row_12(y_in_3, xe_in[12], er_out[12]); Mxnor2 Xor_row_13(y_in_3, xe_in[13], er_out[13]); Mxnor2 Xor_row_14(y_in_3, xe_in[14], er_out[14]); Mxnor2 Xor_row_15(y_in_3, xe_in[15], er_out[15]); Mxnor2 Xor_row_16(y_in_3, xe_in[16], er_out[16]); Mxor2 Xor_row_17(y_in_1, y_in_3, y_d); // h at lsb is inverted Mxnor3 Xor_h_01(y_d, xe_in[1], xe_in[2], hr_out[1]); Mxor3 Xor_h_02(y_d, xe_in[2], xe_in[3], hr_out[2]); Mxor3 Xor_h_03(y_d, xe_in[3], xe_in[4], hr_out[3]); Mxor3 Xor_h_04(y_d, xe_in[4], xe_in[5], hr_out[4]); Mxor3 Xor_h_05(y_d, xe_in[5], xe_in[6], hr_out[5]); Mxor3 Xor_h_06(y_d, xe_in[6], xe_in[7], hr_out[6]); Mxor3 Xor_h_07(y_d, xe_in[7], xe_in[8], hr_out[7]); Mxor3 Xor_h_08(y_d, xe_in[8], xe_in[9], hr_out[8]); Mxor3 Xor_h_09(y_d, xe_in[9], xe_in[10], hr_out[9]); Mxor3 Xor_h_10(y_d, xe_in[10], xe_in[11], hr_out[10]); Mxor3 Xor_h_11(y_d, xe_in[11], xe_in[12], hr_out[11]); Mxor3 Xor_h_12(y_d, xe_in[12], xe_in[13], hr_out[12]); Mxor3 Xor_h_13(y_d, xe_in[13], xe_in[14], hr_out[13]); Mxor3 Xor_h_14(y_d, xe_in[14], xe_in[15], hr_out[14]); Mxor3 Xor_h_15(y_d, xe_in[15], xe_in[16], hr_out[15]); Mxor2 Xor_h_16(y_d, xe_in[16], hr_out[16]); endmodule // Behavioral Model of a 2 inputs And gate module Mand2wd(in1, in2, out); input in1, in2; output out; assign out = (in1 & in2); endmodule // Behavioral Model of a 2 inputs Xor gate module Mxor2wd(in1, in2, out); input in1, in2; output out; assign out = in1 ^ in2; endmodule // Behavioral Model of a 2 inputs Xnor gate module Mxnor2wd(in1, in2, out); input in1, in2; output out; assign out = ~(in1 ^ in2); endmodule // Behavioral Model of a 2 inputs And gate module Mand2(in1, in2, out); input in1, in2; output out; assign out = (in1 & in2); endmodule // Behavioral Model of a 2 inputs Xor gate module Mxor2(in1, in2, out); input in1, in2; output out; assign out = in1 ^ in2; endmodule // Behavioral Model of a 2 inputs Xnor gate module Mxnor2(in1, in2, out); input in1, in2; output out; assign out = ~(in1 ^ in2); endmodule // Behavioral Model of a 3 inputs Xor gate module Mxor3(in1, in2, in3, out); input in1, in2, in3; output out; assign out = in1 ^ in2 ^ in3; endmodule // Behavioral Model of a 3 inputs Xor gate module Mxnor3(in1, in2, in3, out); input in1, in2, in3; output out; assign out = ~(in1 ^ in2 ^ in3); endmodule // Behavioral Model of an inverter gate module Minv(in1, out); input in1; output out; assign out = ~in1; endmodule